1. Field of the Invention
The present invention relates to a multilayer ceramic capacitor and a multilayer-ceramic-capacitor-mounted structure.
2. Description of the Related Art
One example of the prior art documents disclosing a configuration of a multilayer chip capacitor with reduced acoustic noise is Japanese Patent Laying-Open No. 2013-251551. A multilayer chip capacitor described in Japanese Patent Laying-Open No. 2013-251551 includes a ceramic body and an external electrode provided on a surface of the ceramic body. The ceramic body includes a dielectric layer and an internal electrode. The ceramic body includes an active region where the dielectric layer is arranged between the internal electrodes to generate a capacitance, an upper cover layer located above the active region, and a lower cover layer located below the active region. The lower cover layer is thicker than the upper cover layer.
When the thickness of the lower cover layer is increased to reduce the acoustic noise as in the multilayer chip capacitor described in Japanese Patent Laying-Open No. 2013-251551, the degree of reduction in capacitance of the multilayer chip capacitor is large.